1. Field of the Invention
This invention relates to data storage devices, and more particularly to a memory device that can utilize latch cells and tri-state buffering of bit lines depending on enable signals produced from a portion of an address signal at dissimilar times to avoid contention among the buffered bit lines.
2. Description of the Related Art
There is increased use of memories in application specific integrated circuits (ASICs) today, and the trend is for even more memory use per ASIC. There is also a trend for increased use of small memories which are often implemented as latch-based random access memories (LBRAMS). Key issues with LBRAMs include performance and required die area.
A common method to implement memories on ASICs is to use static random access memories (SRAMs) that include an array of bit cells surrounded by logic to read data from, and write data to, the bit cells. In general, SRAM bit cells are organized in groups such that all bit cells in a group are connected to a pair of bit lines. The bit lines are used to write data to the bit cells and to read data from the bit cells. Typically, special sense amplifiers are used to sense small voltage swings on the bit lines to determine whether the bit cell is storing a logic 1 or a logic 0. Using a small voltage swing has the advantage of allowing a smaller bit cell and faster read times. However, the area overhead associated with the sense amplifiers can be a large drawback for small memories. Furthermore, SRAMs are susceptible to many more defects than standard logic and so require special built-in self test (BIST) test logic to test for defects. For smaller memories the die areas required to implement the BIST logic may be larger than the memory itself.
Due to the relatively large die areas required by SRAMs, small memories are often implemented as LBRAMs. A typical LBRAM includes an array of latch cells surrounded by logic to read data from, and write data to, the latch cells. The latch cells are typically organized into groups with all latch cells in a group connected to a common bit line. Unlike SRAM bit lines, latch cell bit lines use standard logic 1 and logic 0 voltage levels. As a result, standard logic can be connected directly to the bit lines to read the data. This reduces the area overhead to implement the memory, and for small memories the area of an LBRAM is much smaller than a comparable SRAM.
The main drawback with using full voltage swings on the bit lines is that transitions from one logic level to another take longer, negatively impacting memory performance. As a result of the slow transitions, known LBRAMs are often slower than, or at best match the performance of, comparable SRAMs. However, as latch cells are quite similar to standard logic, and full voltage swings are used on the bit lines, LBRAMs are not susceptible to any more defects than standard logic cells, and the BIST logic overhead required with SRAMs can be avoided. For example, LBRAMs can be smaller than comparable SRAMs at memory sizes up to 8K total data bits.
It would be beneficial to have a random access memory (RAM) structure that has a read access time that is sufficiently less than known LBRAM structures and/or requires a smaller die area than known LBRAM structures.